SRTCR_EN=DISABLED, MCR_EN=DISABLED, OSCB=NOT_BYPASSED
SNVS_LP Security Events Configuration Register
| SRTCR_EN | SRTC Rollover Enable When set, an SRTC rollover event generates an LP security violation. 0 (DISABLED): SRTC rollover is disabled. 1 (ENABLED): SRTC rollover is enabled. |
| MCR_EN | MC Rollover Enable When set, an MC Rollover event generates an LP security violation. 0 (DISABLED): MC rollover is disabled. 1 (ENABLED): MC rollover is enabled. |
| PFD_OBSERV | System Power Fail Detector (PFD) Observability Flop The asynchronous reset input of this flop is connected directly to the inverted output of the PFD analog circuitry (external to the SNVS block) |
| POR_OBSERV | Power On Reset (POR) Observability Flop The asynchronous reset input of this flop is connected directly to the output of the POR analog circuitry (external to the SNVS |
| LTDC | Low Temp Detect Configuration These configuration bits are wired as an output of the module. |
| HTDC | High Temperature Detect Configuration These configuration bits are wired as an output of the module |
| VRC | Voltage Reference Configuration These configuration bits are wired as an output of the module. |
| OSCB | Oscillator Bypass When OSCB=1 the osc_bypass signal is asserted 0 (NOT_BYPASSED): Normal SRTC clock oscillator not bypassed. 1 (BYPASSED): Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. |